Qwen3.8 Generated Engineering Artifacts
These SVGs were generated end to end by the Qwen3.8 27B Q4_K_M runtime in CKE on one Ryzen 9 9950X3D CPU. They are retained both as useful engineering diagrams and as inspectable model-quality evidence: each artifact is standalone XML, contains no scripts or external references, and can be opened directly in a browser.
A valid, useful SVG is model-output evidence, not by itself a numerical or performance certification. Text and measurements inside each diagram reflect the dossier supplied to that generation. The Model + Kernel Matrix, X-Ray reports, and committed benchmark artifacts remain authoritative for promoted claims.
Measured Generation Envelope
| Property | Measured result |
|---|---|
| Runtime | Qwen3.8 27B Q4_K_M, CKE v8 generated C, 16 pinned physical cores |
| Long-context inputs | Six complete 131,072-token inputs; each stopped on the model EOS token |
| Generated output | 7,998 to 16,950 tokens per long-context artifact |
| Prefill | 32.37 to 32.71 tok/s across the six runs |
| Decode | 1.36 to 1.41 tok/s across the six runs |
| Peak resident memory | Approximately 50.6 GiB |
| SIMD RoPE artifact | 1,152-token prompt, 24,227-token answer, 3.1 tok/s decode, 15.02 average active cores |
| Numerical certification | Separate 4,000/4,000 full-vocabulary rows and 4,011 internal rows bit-exact to llama.cpp |
Long-Context System Overview
A single-page synthesis of the GGUF-to-generated-C pipeline, memory hierarchy, recurrent/full-attention schedule, ZIP research direction, Memory Tetris, planner-owned scratch, and X-Ray evidence.
Download SVGSHA-256 15df1242411b32a0...
RoPE Across a 128K Hybrid Context
Visualizes absolute-position continuity through chunked prefill, the recurrent-to-full-attention cadence, grouped-query cache addressing, X-Ray failure modes, and planned long-context work.
Download SVGSHA-256 a692ea875c0dddbe...
Qwen3.8 CPU Execution Path
Connects the model circuit, quantized representations, SIMD path, deterministic output-range reductions, persistent workers, planner scratch, utilization, and follow-up optimization targets.
Download SVGSHA-256 7954e1212f7fe25b...
Theory of Constraints
Shows the intended flow from NVMe through DRAM and cache to SIMD workers, contrasting exposed stop-and-go stalls with overlapped compute and memory work.
Download SVGSHA-256 c376811abd8b6343...
CKE and llama.cpp Comparison Discipline
Documents the matched-run conditions, consumed-token hashes, full-logit checks, X-Ray localization, occupancy accounting, provider timing, and claim boundaries required for a fair comparison.
Download SVGSHA-256 4f958d4811a1cafa...
Core Saturation and Scheduling
Turns the observed worker occupancy into a scheduling diagram: persistent threads, queue depth, barriers, deterministic reductions, tile ownership, and the decode imbalance that remains diagnostic rather than a final causal claim.
Download SVGSHA-256 11d3067256e32229...
Split-Half FP32 RoPE SIMD
A kernel-level diagram of validation, split-half layout, AVX2 lanes, operation order, in-place safety, scalar tail handling, and the no-allocation call contract.
Download SVGSHA-256 57cd78c57efc79e9...
Validation Notes
- All seven published files parse as XML, use an SVG root and viewBox, and contain no script or external reference.
- Two earlier candidates were rejected because they were malformed XML; they are not published here.
- The RoPE SIMD quality gate marked its run failed because two required literal labels used different wording. The resulting SVG itself is valid and retained for human review.
- Generation quality, numerical parity, and performance remain three separate scorecard dimensions.