Access Before Ownership
CAD $0–$2,000
Remote machine access, short-term loaners, cloud or lab credits, profiler access, and engineering contacts. This stage validates fixtures and reduces the risk of purchasing the wrong configuration.
Open hardware evidence program
Help CKE prove CPU AI on hardware engineers can inspect and own.
C-Kernel-Engine needs more than benchmark claims. It needs repeatable measurements across SIMD generations, memory topologies, NUMA domains, and real network links. Support expands the laboratory while keeping the code, methods, limitations, and publishable results open.
Public program target
Build the full CPU AI evidence laboratory in stages
CAD $30,000
The target is a ceiling for the complete multi-year program, not a requirement to spend everything immediately. Each CAD $5,000 milestone releases a more capable evidence lane only after the previous stage produces inspectable results.
$5Kfirst 636 node
$10Kmatched 636 pair
$15Kmemory + storage
$20Knetwork + metering
$25K8-channel upgrade
$30Kfull evidence program
Current funding must be reported manually. Until GitHub Sponsors and in-kind contributions are reconciled into a public ledger, these markers describe capability gates rather than claiming money raised.
The Immediate Goal
Founder funding establishes matched Xeon 636 nodes for native AMX BF16, AVX-512/VNNI, four-channel memory, and direct-network experiments. Sponsor support then unlocks the Xeon 600 platform's full eight-channel path through compatible 650/670-class processor upgrades and four additional matched RDIMMs per node. The resulting four-channel-versus-eight-channel comparison becomes a published experiment rather than an assumed benefit.
One Xeon 636 Evidence Node
CAD $5,500–$8,000
A balanced workstation with ECC memory across the four channels exposed by the 630-series CPU, NVMe storage, sustained cooling, power measurement, and room for a high-speed NIC. It unlocks native AMX BF16 and controlled memory work.
Matched Xeon 636 Lab
CAD $12,500–$19,000 total
A second matched node plus two 100GbE-capable NICs, a direct DAC link, storage, metering, and contingencies. A switch is deferred until a third node creates a measured need.
Primary Sponsorship Target: The Eight-Channel Upgrade
The W890 workstation platform has eight DIMM slots, but ASUS specifies that a Xeon 630-series processor enables only channels A, C, E, and G. The most valuable hardware sponsorship is therefore two compatible Xeon 650/670-class processors plus four additional matched RDIMMs per node. CKE will publish the controlled four-channel-versus-eight-channel result across memory bandwidth, prefill, decode, AMX BF16 kernels, power, NUMA behavior, and distributed workloads. Final CPU selection will also score cache per core, core count, topology, price, and availability; channel count alone will not decide the configuration.
Budget discipline: these are planning ranges, not a final bill of materials. CPU availability, ECC-memory pricing, tax, cooling, chassis, PSU connectors, NIC provenance, and warranty must be quoted before purchase. Funds are released by stage; a second node is not purchased until the first-node evidence pipeline is working.
What the Laboratory Will Test
| Experiment lane | Measurements | Required evidence |
|---|---|---|
| AMX BF16 kernels | Tile utilization, conversion boundaries, accumulation semantics, throughput, and parity against PyTorch | Commands, shapes, ISA detection, assembly/profiler artifacts, numerical tolerances |
| AVX-512 and VNNI | FP32 and quantized GEMM/GEMV, attention, reductions, fusion, cache behavior | AVX2 baseline, compiler flags, warmups, repeats, end-to-end impact |
| Memory channels | One through fully populated channel configurations where practical; bandwidth, latency, and model throughput | DIMM topology, frequency, NUMA map, measured STREAM-like baseline and real CKE workload |
| NUMA placement | First-touch, interleave, binding, page size, thread affinity, local versus remote access | numactl topology, allocation policy, counters, RSS, latency and throughput |
| Single-node inference | Prefill, decode, time to first token, RSS, power, thermals, numerical parity | Model hash, quantization, context, batch, threads, commit, reference runtime |
| Bounded training | Forward/backward parity, optimizer state, memory budget, BF16/FP32 behavior and step time | Explicit supported circuit and dataset; no extrapolation to frontier-scale training |
| Distributed execution | One-node versus two-node scaling, tensor/pipeline partitioning, communication overlap, replicated versus sharded state | Topology, payload sizes, synchronization, transport, efficiency and failure modes |
| Network crossover | 10/25/100GbE or available links; sockets/MPI and RDMA where supported | Wire rate, CPU cost, message-size sweep, latency, bandwidth and end-to-end model effect |
| Power and TCO | Idle, kernel, model, and distributed wall power; energy per workload | Meter model, measurement interval, local electricity assumption and dated BOM |
| Portability | Core i7, Xeon generations, ARM/NEON and future AMD/Arm server access | Same fixtures and canonical output boundaries; architecture-specific limitations retained |
What Support Produces
Reproducible code
Kernel and runtime patches, parity gates, benchmark commands, machine-readable result records, and versioned hardware metadata.
Inspectable evidence
VTune, Advisor, perf, assembly, memory, network, power, and end-to-end reports with failures and negative results retained.
Public interpretation
Source-linked documentation, ShivasNotes articles, diagrams, and videos that explain what changed, why it matters, and where the result does not generalize.
Ways to Contribute
- Remote access: provide a controlled shell on relevant Xeon, AMD EPYC, Arm server, or embedded hardware.
- Loaner hardware: lend a workstation, CPU, memory kit, NIC, power meter, or embedded target for a defined test period.
- Components or discounts: reduce the cost of matched CPUs, ECC memory, storage, networking, chassis, cooling, and measurement equipment.
- Engineering collaboration: help validate BIOS, compiler, ISA, memory, network, or profiler assumptions with a named technical contact.
- Funded investigation: sponsor a bounded model/hardware qualification, numerical investigation, kernel path, or benchmark lane.
- Financial contribution: fund a published stage or a clearly identified component after the bill of materials is confirmed.
Use GitHub Sponsors for direct financial support. Use ShivasNotes Work With Us for a paid private investigation with bounded deliverables. Hardware vendors and laboratories can contact Anthony Shivakumar about loaners, remote access, parts, or discounts.
Evidence and Disclosure Contract
Sponsorship does not purchase a favorable conclusion. Every published result identifies hardware, firmware where available, detected ISA, memory topology, operating system, compiler, CKE commit, model hash, quantization, workload, thread policy, commands, warmups, repetitions, reference backend, date, and known limitations.
Financial support, loaners, discounts, credits, and vendor engineering assistance are disclosed beside affected results. Sponsors may review factual hardware details before publication but cannot suppress reproducible negative findings or rewrite conclusions. Security-sensitive credentials and legitimately confidential information are excluded from public artifacts.
Release Gates
- Publish the final configuration and experiment manifest before purchasing the second node.
- Bring up the first node, verify cooling, power, ECC topology, ISA exposure, and baseline stability.
- Close numerical parity for the selected AMX BF16 and AVX-512 paths before performance claims.
- Publish at least one complete single-node evidence report and reusable result schema.
- Add the matched node and direct network only after distributed CKE has an executable test plan.
- Promote distributed CPU scaling from research thesis to demonstrated capability only after measured results.
Start With a Specific Contribution
Send the hardware model, access constraints, support type, available dates, and the question you want tested to anthony.shivakumar@antshiv.com. For paid engineering work with private inputs and bounded deliverables, use the Work With Us page.